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U3600BM
Single Chip Cordless Telephone IC
Description
The programmable single chip multi channel cordless phone IC includes all necessary low frequency parts such as microphone- and earphone amplifier, compander, power-supply management, as well as all RF parts such as IF converter, FM demodulator, RSSI, oscillators and PLL. Several gains and mutes in transmit and receive direction are controlled by serial bus while compander can be bypassed.
Features
D All functions and channel selections are controlled by serial bus RF Part D All oscillators and PLL integrated D IF converter D FM demodulator D RSSI Low Frequency Part D Asymmetrical input of microphone amplifier D Asymmetrical output of earpiece amplifier D Compander D Power supply management D Serial bus Application: CT0 standard Narrow band voice and data transmitting / receiving systems
MIX2IN MIX2O OSCGND MIX1O MIX2GND XCK VAF 39 37 36 34 38 33 35 Crystal Oscillator Mixer2
Block Diagram
MIX1IN2 41 42 GNDLO MIX1IN1 40 IFIN1 32 IFIN2 31 IF Amp RSSI MUXDA D A - Bias Bat low Detector DATRX + ETC 30 EXIN 29 Expander Ear Amp 27 Mixer1 28 RECO1 RECO2
fLO LO2 LO1 43 44 VCO3 :2 fLO fLO :N fRef3 Serial Bus :K
Demo- dulator
26
RXO
sin PCLO 1 1
cos
(3)
Phase Comparator
25 + - 1.5V - Mic + 24
DAIN
MIC
MixerT +45 -45
:D2 :D1 :M12 :M12 (2) f Ref2 :2 Phase Comparator
: PM )
(1)
:D3 fMod
QM 223
VRMIC 23 MICO 22 COIN 21 20 CTC COUT
:10 :M :2 fRef1 + Spl 1.5V Limiter Amp - 13 14 15 16 17 18 Compressor
RFOGND RFO RFOVB
2 3 4 5 AGND 6 VBIAS VCO2 Loop Filter 7 VRF
VCO1 8 9 10
Phase Comparator 11 VDD 12
19
LIMIN
MLF LFGND MODIN (2): PLL2: Mixer PLL
(1): PLL1: Modulator PLL
TXO OPOUT OPIN DACO (3): PLL3: Local oscillator (LO) PLL
VSS D C
Figure 1. Block diagram
Rev.A1, 14-Jun-00
1 (34)
Preliminary Information
U3600BM
Ordering Information
Extended Type Number U3600BM-MFN U3600BM-MFNG3 Package SSO44 SSO44 Tube Taped and reeled Remarks
Pin Description
RFOGND RFO RFOVB AGND VBIAS VRF MLF LFGND
2 3 4 5 6 7 8 9
43 LO2 42 GNDLO 41 MIX1IN2 40 MIX1IN1 39 MIX1O 38 OSCGND 37 XCK 36 VAF 35 MIX2O 34 33 32 MIX2GND MIX2IN IFIN1
MODIN 10 VDD VSS 11 12
D 13 C DACO OPOUT OPIN TXO LIMIN COUT CTC COIN 14 15 16 17 18 19 20 21 22
31 IFIN2 30 ETC 29 EXIN 28 RECO1 27 RECO2 26 RXO 25 DAIN 24 MIC 23 MICO
Figure 2. Pinning
2 (34)
Preliminary Information
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5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PCLO
1
44 LO1
Pin 1 2 3 4
Function Phase comparator local oscillator RF transmit output ground RF transmit output Power supply input of RF transmit output buffer AGND Analog ground for RF part VBIAS Decoupling capacitor of current reference VRF Supply voltage for RF part MLF Modulator loop filter LFGND Modulator loop filter ground MODIN Modulator input VDD Supply voltage output for peripherals and internal supply of digital part VSS Ground for LF analog and digital D Data input of serial bus C Clock input of serial bus DACO D/A and data comparator output OPOUT Operational amplifier output OPIN Operational amplifier input (inverting) TXO Output of limiter amplifier LIMIN Limiter input COUT Compressor output CTC Compressor time constant control analog output COIN Compressor input MICOAAAAAAAAAAAA Microphone amplifier output MIC Inverting input of microphone amplifier DAIN Data comparator input RXO Output of demodulator RECO2 Symmetrical output of receive amplifier RECO1 EXIN Expander input ETC Expander time constant control analog output IFIN2 Symmetrical input of IF amplifier IFIN1 MIX2IN Input of Mixer2 MIX2GND IF amplifier and Mixer2 ground MIX2O Mixer2 output VAF Supply voltage for AF/IF parts XCK Crystal oscillator input 11.15 MHz OSCGND Oscillator ground MIX1O Output of Mixer1 MIX1IN1 Symmetrical input of MIxer1 MIX1IN2 GNDLO Ground of LO LO2 Tank elements for LO are connected to these pins LO1
Symbol PCLO RFOGND RFO RFOVB
Rev.A1, 14-Jun-00
U3600BM
System Description
Radio frequency IC for analog cordless telephone application in 26/50 MHz band (CTO standard). The IC performs full duplex communication. The transmitting and receiving frequency are depending on whether the IC is used in the handset or in the base station. Frequency converter comprise a FM transmitter with switchable output power and first receiver mixer in the same unit. A two wire bus interface can be used for the frequency control as well as for switching the transmitter power amplifier and the receiver. Fine frequency adjust of reference quartz oscillator is programmable. The receive part is designed for a double conversion architecture. The incoming radio frequency signal will be filtered and amplified before reaching the first mixer. At this stage the RF signal will be converted down to the first intermediate frequency (10.7 MHz) by using a crystal oscillator (LO1). The transmit part contains two PLL controlled VCOs. The frequency modulation is accomplished by superposing the incoming audio signal on the PLL control voltage. Final frequency is a product of mixing VCO1 with first local oscillator of receiver part (VCO3). The FM modulated carrier is amplified by externals power amplifier before entering the output filter and the antenna connector.
Adjustment for VCO3
In order to increase the adjustment range of VCO3 with fixed external tank elements and/or for "band switching", especially for US frequencies, VCO3 has programmable capacitors inside. These capacitors can be added by serial bus (FA3 [4:0]) between LO1 and LO2. There are 31 steps available, every step adding a capacitor of 0.5pF.
Speed-up of the Loop Filter of PLL1 ("Modulator PLL")
To have a fast locking time for the modulator loop there is a precharge and a speed-up mode for the external loop filter. During receive mode (VCO3 enabled, VCO1 disabled) the modulator loop filter is precharged to about half of the internally regulated 2.5 V charge-pump voltage. During the first 30 ms after enabling VCO1 the modulator phase comparator is in speed-up mode. In this mode the current of the pase comparator which charges the loop filter is much larger than in normal mode. Additionally to the automatically switched 30 ms speed-up mode, the speed-up can be activated for any time by setting the bit SU1.
Adjustments for VCO1 and VCO2
To be able to use a wide frequency range for the VCOs (i.e., VCO2 26.3 MHz to 49.9 MHz) the two internal VCOs (VCO1 and VCO2, i.e., the VCOs of the transmit part) have a rough adjust and a fine adjust to increase the frequency range given by the phase comparator. The rough adjusts for these VCOs are correlated with the country setting. For every country there are two sets of VCO rough adjust settings, one for the base and one for the handset . See tables at channels frequencies and dividers. To compensate the variation in production there is a fine adjust for each of the VCOs. The fine adjusts of the internal VCOs could be set manually (for test purposes) or set by the automatic mode. Theoretically the sign of the changing (increase/ decrease when the voltage of the phase comparator is to high) is selectable, but we need value 1 () in all cases. Setting VCO1 (VCO2) under normal conditions: EAFA1 (EAFA2) = 1, automatic fine adjust VCO1(VCO2) enabled SAFA1 (SAFA2) = 1, sign of auto fine adjustment of VCO1 (VCO2) = 1.
Speed-up of the Loop Filter of PLL3 ("1st. LO.")
Similiar to PLL1 there is also a possibility to increase the locking speed of PLL3. This can be done by setting the bit SU3. Having done this, the charge pump at the output of the phase comparator has a bigger current capability and therefore charges the external capacitors faster.
Adjustment of the Modulator Gain
To fulfil the different requirements of the different countries three conversion gains of the modulator are selectable by the bits GMOD [1:0] (R6: D2, D3). Country settings see tables at channel frequencies and dividers. Ranges see electrical characteristics at RF transmitter.
Rev.A1, 14-Jun-00
3 (34)
Preliminary Information
U3600BM
Modulator PLL
The fractional divider has been chosen to increase the reference frequency of the modulator PLL. 557.5 kHz + f Mod P1 ) Q1 223
Serial Bus Interface
The circuit is remoted by an external microcontroller through the serial bus. The data is an 12-bit word: A0 - A3: address of the destination register (0 to 15)
P1: integer part of the fractional divider (M = 1) Q1: fractional part of the fractional divider (M = 1) Q 1 + 223 f Mod * P1 557.5 kHz
D7 - D0: contents of register The data line must be stable when the clock is high and data must be serially shifted. After 12 clock periods, the transfer to the destination register is (internally) generated by a low to high transition of the data line when the clock is high.
223 + 557.5 kHz 2.5 kHz The frequency step 2.5 kHz is a fraction of the reference frequency 557.5 kHz. In fact, the fractional divider divides Q1 times by (P1 + 1) and (223 - Q1) times by P1 during 223 cycles. Q1 (P1 ) 1) ) (223 * Q1) P 1 Q + P1 ) 1 223 223
Data Microprocessor Clock
D C
For each comparison cycle (fRef1 = 557.5 kHz), the accumulator content is incremented by the Q1 value and the divider divides by the P1 value. When the accumulator value reaches or exceeds 223, the divider divides by the value (P1 + 1). Then, the accumulator holds the excess value (accumulator value - 223). After 223 cycles, the correct division is executed.
96 11787
Figure 3.
Data (D)
D0
D1
D2
A0
A1
A2
A3
Clock (C) 1st word
16253
2nd word Transfer condition
Word transmission Figure 4. Serial bus transmission
4 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
Data 4 Clock 8
0 Address Decoder 15 128 Latches
14994
Commands
Figure 5.
Data (D) A1 A2 A3 D0
Clock (C) tsud thd tch
Figure 6.
tcl
teon
teh
teoff
16254
Rev.A1, 14-Jun-00
5 (34)
Preliminary Information
U3600BM
Content of Internal Registers
The register have the following structure: D7 D6 D5 D4 D3 D2 D1 D0
R0: Reference for D/A converter MUXDA MUXDA: DA(0:6): DA6 DA5 DA4 DA3 DA2 DA1 DA0
D/A multiplexing VBAT / RSSI Reference voltage D/A
R1: Gain of earpeace amplifier and demodulator GEA4 GEA[0:4]: GDEM: GEA3 GEA2 GEA1 GEA0 GDEM free free
Gain of earpeace amplifier; "0" is LSB, "4" is MSB Demodulator gain (1=low gain)
R2: Switches and mutes for receive and data reception DATRX DATRX: BEXP: EEA: ERXO: ERX1: ERXHF: MRX: ERX2: BEXP EEA ERXO ERX1 ERXHF MRX ERX2
Switch data comparator output to "DACO"-pin Bypass expander Enable earpiece amplifier Enable RXO output driver Enable RX low frequency part 1 Enable Mixer2 and IF-amplifier Mute RX low frequency path (expander) keeping circuit enabled Enable RX low frequency part 2 (expander)
R3: Switches and mutes for transmit and power managemant PDVDD PDVDD: RBAT: MTX: ETX: RBAT free free free free MTX ETX
Enable pull-down transistor in power-down mode Battery detection high/ low range Mute TX low frequency path (compressor) keeping circuit enabled Enable TX low frequency part
R4: free (not used, for future extensions) free free free free free free free free
R5: Gain VCO2 free KV2[1:3]: M12: free KV23 KV22 KV21 M12 free free
Gain of VCO2 Double phase comparator frequency of PLL2
6 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
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GMOD1 GMOD0 SU1 (TM) ETXO: M1CP: FRMT: IMIXI: GMOD[0:1]: SU1: (TM): Enable HF-transmit output Changes 1 dB compression point and current consumption of Mixer1 ("0" -> high, "1" -> low) Output frequency range of MixerT Invert inputs of phase comparator in PLL2 Modulation gain of VCO1 Speed-up phase comparator for PLL1 Enable the internal test mode. It is mandatory that TM is kept to "0"! (if not 0, the circuit will not work as expected or described here in this paper) R7: PLL1 setting DR1I1 DR1I[0:1]: RA1[0:1]: DV1I[0:3]: DR1I0 RA11 RA10 DV1I3 DV1I2 DV1I1 DV1I0 Additional divider reference frequency PLL1 Rough adjustment VCO1 Divider setting PLL1 integer part; "0" is LSB, "3" is MSB
R6: Miscellaneus settings in synthesizer part ETXO M1CP FRMT IMIXI
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DV1F4 DV1F3 DV1F2 DV1F1 DV1F0 DV1F[0:7]: Divider setting PLL1 fractional part; "0" is LSB, "7" is MSB R9: Divider PLL3 LSBs DV3I7 DV3I6
R8: Divider PLL1 fractional part DV1F7 DV1F6 DV1F5
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DV3I5 DV3I4 DV3I3 DV3I2 DV3I1 DV3I0 R10: Divider PLL3 MSBs and MSB of VCO3 fine adjustment FA34 DV3I14 DV3I13 DV3I12 DV3I11 DV3I10 DV3I9 DV3I8 FA34: Fine adjustment VCO3 (frequency reduction) MSB DV1I[0:14]: Divider setting PLL3 integer part; "0" is LSB, "14" is MSB
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FA30 AMIX2 AMIX1 RA21 RA20 FA3[0:4]: Fine adjustment of VCO3 (frequency reduction); "0" is LSB, "4" is MSB AMIX[1:2]: Lengthening antibacklash signal PLL2 RA2[1:0]: Rough adjustment VCO2 R12: Divider for country setting, fine adjustment oscillator
R11: Setting PLL2 and VCO3 FA33 FA32 FA31
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FAOS2 FAOS1 FAOS0 D31 D30 D20 D11 D10 FAOS[0:2]: D3[0:1]: D20: D1[0:1]: Fine adjustment of crystal oscillator (frequency reduction); "0" is LSB, "2" is MSB Setting divider D3 Setting divider D2 Setting divider D1 Rev.A1, 14-Jun-00 7 (34)
Preliminary Information
U3600BM
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FA14 FA13 FA12 FA11 FA10 EVCO1: SAFA1: EAFA1: FA1(0:4): Enable VCO1 Sign for automatic fine adjustment of VCO1 Enable automatic fine adjustment of VCO1 Manual fine adjustment of VCO1 (frequency reduction); "0" is LSB, "4" is MSB
R13: VCO1 enable and fine adjustment EVCO1 SAFA1 EAFA1
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FA24 FA23 FA22 FA21 FA20 EVCO2: SAFA2: EAFA2: FA2(0:4): Enable VCO2 and MixerT Sign for automatic fine adjustment of VCO2 Enable automatic fine adjustment of VCO2 Manual fine adjustment of VCO2 (frtequency reduction); "0" is LSB, "4" is MSB R15: VCO3 enable, speed-up and referencq frequency, crystal oscillator enable
R14: VCO2 enable and fine adjustment EVCO2 SAFA2 EAFA2
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EVCO3 EOSC SU3 E25K E12K5 E10K E6K25 E5K EVCO3: EOSC: SU3: E25K: E12K5: E10K: E6K25: E5K: Enable VCO3 and Mixer1 Enable crystal oscillator (11.15 MHz) Speed-up phase comparator for PLL3 Selection phase comparator frequency Selection phase comparator frequency Selection phase comparator frequency Selection phase comparator frequency Selection phase comparator frequency for for for for for PLL3: PLL3: PLL3: PLL3: PLL3: fRef3 = 25 kHz fRef3 = 12.5 kHz fRef3 = 10 kHz fRef3 = 6.25 kHz fRef3 = 5 kHz E5K, E6K25, E10K, E15K5, E25K = 0: Selection phase comparator frequency for PLL3: fRef3 = 2.5 kHz
Absolute Maximum Ratings
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Supply voltage Junction temperature Ambient temperature Storage temperature Power dissipation Tamb = 60C
Parameters
Symbol VBatt, VCC Tj Tamb Tstg Ptot
Value 5.5 +125 -25 to +75 -50 to +125 0.9
Unit V C C C W
Thermal Resistance
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Junction ambient 8 (34) Rev.A1, 14-Jun-00
Parameters SSO44
Symbol RthJA
Value 70
Unit K/W
Preliminary Information
U3600BM
Electrical Characteristics
Tamb = +25C, VRF = VAF = RFOVB = 3.6 V, all bits set to "0", unless otherwise specified. Test circuit, see figure 7.
Parameters Power supply Operating voltage range Current consumption Operating current in inactive mode (low voltage) Operating current in standby mode Operating current in RX mode "waiting for RSSI" Operating current in RX mode "receiving data" Operating current in conversation mode: all blocks enabled Test Conditions Symbol Min. 3.1 30 30 Typ. 3.6 65 Max. 5.2 85 Unit V
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VRF = VAF = RFOVB = 2.9 V VDD = 0 V VRF = VAF = RFOVB = 3.6 V A A 100 7.5 8.5 20 350 ERXHF = EVCO3 = EOSC = 1 ERXHF = EVCO3 = EOSC = ERX1 = ERXO = 1 ERXHF = EVCO3 = EOSC = ERX1 = ERXO = ERX2 = EEA = EVCO2 = ETXO = 1 no load at RFO Pin 3 Output high SB127 = 1, SB119 = 0 2.38 1.15 10.4 11.5 29 mA mA mA
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Charge Pump of PLL1 Charge pump output voltage Precharge voltage at the loop filter Charge pump output current in speed-up mode Charge pump output current 2.5 1.4 2.63 1.65 V V
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2.38 220 -420 80 -160 -50 20 2.5 2.63 420 -220 160 -80 +50 50 V A A A A nA
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Charge pump leakage current Charge Pump of PLL3 Charge pump output voltage Output high Charge pump output current in VPCLO = 1.25 V, output low speed-up mode VPCLO = 1.25 V, output high Charge pump output current VPCLO = 1.25 V, output low VPCLO = 1.25 V, output high Charge pump leakage current VPCLO = 1.25 V, output tristate Receiver Input Mixer (Mixer1) EVCO3 = EOSC = 1 Input frequency range Output frequency Input resistance MIX1IN1 / MIX1IN2 to GND Input capacitance MIX1IN1 / MIX1IN2 to GND Output impedance MIX1O Voltage gain MIX1IN1/2 -> MIX1O "Loaded" (330 W with ser.Cap.) "Unloaded" Input noise voltage Input 1-dB compression point "Loaded" (330 W with ser.Cap.) M1CP=0 M1CP=1 "unloaded" M1CP=1 Third order input intercept "Loaded" (330 W with ser.Cap.) point M1CP=0
VMLF = 1.25 V, output low VMLF = 1.25 V, output high VMLF = 1.25 V, output low VMLF = 1.25 V, output high VMLF = 1.25 V, output tristate
190 -400 4.3 -8 -150
6.2 -6.2
400 -190 8 -4.3 +150
A A A A nA
210
10,7 3.0 3.5 330 11.5 17.5 9 140 40 100 430
390
MHz MHz kW pF W
dB dB nV Hz-1/2 mV mV mV mV
Rev.A1, 14-Jun-00
9 (34)
Preliminary Information
U3600BM
Parameters IF Mixer (Mixer2) Input resistance Input capacitance Output impedance Voltage gain Test Conditions Symbol Min. 2.0 2.5 1200 13 32 Typ. 3.0 3 1500 15 Max. 4.0 3.5 1800 17 Unit kW pF W dB
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EOSC = ERXHF = 1; input frequency: 10.7 MHz MIX2IN to GND MIX2IN to GND MIX2O MIX2IN -> MIX2O "Loaded" (1500 W with ser.Cap.) Input 1-dB compression point "Loaded" (1500 W with ser.Cap.) mV
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VIF = 25.4 V, f = 450 kHz increase RSSI level again until mean of sampled signal at DACO is 0.5. RSSI-level = ION1 RSSI-sensitivity = ION1-ION0 RSSI input voltage dynamic range RSSI level number of programmable steps*) RSSI level step size in the logarithmic region 65 127 0.35 0.46 0.6 dB dB dB
Third order input intercept 80 mV "Loaded" (1500 W with ser.Cap.) point IF Amplifier and Demodulator ERXHF=1, ERX1=1, ERXO=1; Input signal: 450 kHz, 500 mV, FM-modulation frequency = 1 kHz Recovered audio at RXO, GDEM=0 180 mV/kHz demodulator gain GDEM=1 90 mV/kHz AM rejection ratio 30% AM, 2.5 kHz FM 35 dB Expander ERX2 = 1; 470 nF from ETC to GND (VSS) Gain reference level = G.R.L. 70 80 90 mVrms (gain = 0 dB) Gain versus input signal level VEXIN = 10 dB less than G.R.L. -11 -10 -9 dB ("gain tracking") VEXIN = 20 dB less than G.R.L. -21 -20 -19 dB VEXIN = 30 dB less than G.R.L. -35 -30 -25 dB Attack time VEXIN = step 25 mV -> 50 mV 16 ms measure time after step, when output voltage has 0.75 times of final value Release time VEXIN = step 50 mV -> 25 mV 16 ms measure time after step, when output voltage has 1.5 times of final value Input resistance 9.5 15 kW Earpiece Amplifier EEA = 1, ERX2 = 1, BEXP = 1; apply input voltage to EXIN; measure differentially at RECO1/2 Minimum gain GEA[4:0]=0 0 1 2 dB Medium gain GEA[4:0]=16 16 17 18 dB Maximum gain GEA[4:0]=31 31 32 33 dB Gain adjust step 0.8 1 1.2 dB Output voltage swing 4.8 5 Vpp Maximum gain; 1 kW load; increase input voltage until distortion 5% Input resistance 7.3 12.5 kW IF Amplifier: RSSI Input frequency ERXHF=1 450 kHz Input resistance 1.6 2.0 2.5 kW RSSI sensitivity VIF = 0 V 1 starting from 0 increase RSSI-level until mean of sampled signal at DACO is 0.5. RSSI-level = ION0
10 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
*) RSSI Level Programming (Typical Values)
Input Voltage VIF (V) 0 25.4 42.4 424 4240 42400 RSSI Level (Decimal) 5 8 14 54 97 111
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Data Comparator Hysteresis Threshold voltage Input impedance
ERX1 = DATRX = 1
Parameters
Test Conditions
Symbol
Min.
Typ. 50
Max.
Unit mV V V V k k
1.5 3.5 0.1 6
DAIN
100
Output high voltage Output low voltage Output impedance Battery Switch "Off" threshold
DACO, without load (CMOS-output -> full swing) DACO, without load (CMOS-output -> full swing) DACO Decrease VBAT until internal switch between VBAT and VDD becomes high ohmic ("off") 2.85
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2.95 3.1 V "On" threshold Hysteresis "Off"-leakage current Switch "On"-resistance Battery Management MUXDA = 1 Max bat low Min bat low over switch Max bat high Min bat high Adjust step Max - Min Microphone Amplifier Open loop gain ETX=1 DA[6:0] = 127, RBAT = 1 DA[6:0] = 27, RBAT = 1 DA[6:0] = 0, RBAT = 0 DA[6:0] = 127, RBAT = 0 3.7 3.95 3.2 4.1 7.5 952.5 80 3 5.05 Increase VBAT until internal switch between VBAT and VDD becomes low ohmic ("on") Difference between on and off threshold 3.1 3.2 3.35 V 250 10 50 4.1 mV A W V V V V mV mV dB
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3.05 4.75 3.83 3.5 852.5 3.35 5.25 4.27 11.5 1052.5
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Gain bandwidth product MHz Input noise voltage, BW = 300 Hz to 3.4 kHz, psophometrically weighted 0.8 2 Vrmsp
Rev.A1, 14-Jun-00
11 (34)
Preliminary Information
U3600BM
Parameters Compressor Gain reference level = G.R.L. (gain = 0 dB) Test Conditions Symbol Min. 298 9 19 22 Typ. 316 10 20 25 30 Max. 340 11 21 28 Unit mVrms
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ETX=1; 470 nF from CTC to GND (VSS) Gain versus input signal level ("gain tracking") VCOIN = 20 dB less than G.R.L. VCOIN = 40 dB less than G.R.L. VCOIN = 50 dB less than G.R.L. VCOIN = 60 dB less than G.R.L dB Attack time VCOIN = step 31.6 mV -> 126 mV, (-30 dBV -> -18 dBV) measure time after step, when output voltage has 1.5 times of final value VCOIN = step 126 mV -> 31.6 mV (-18 dBV -> -30 dBV) measure time after step, when output voltage has 0.75 times of final value 14 ETX = 1 3.5 ms Release time 14.4 ms Input resistance Splatter Amplifier Open loop gain 19.5 90 26 kW dB
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Gain bandwidth product 150 kHz Maximum output voltage swing Limiter Amplifier Gain for signals below limitation 2.4 Vpp ETX = 1, Tj = 25C LIMIN -> TXO, 20 mVRMS applied to LIMIN (AC coupled) LIMIN -> TXO, 20 mVRMS applied to LIMIN (AC coupled) 26 dB % Distortion for signals below limitation 2 Maximm output voltage swing (above limitation, clipping) Input resistance at LIMIN 1.8 15 2.1 20 2.35 25 Vpp k Remark: The gain and maximum output voltage swing of the limiter amplifier changes with temperature to compensate the temperature dependancy of MODIN ("tx conversion gain" of RF transmit part), fundamentally determined by the structure of the circuitry. RF Transmitter ETXO = EVCO1 = EVCO2 = EVCO3 = EOSC = 1; Tj = 25C Load = 200 MODIN input impedance RFO output impedance RFO output voltage level TX conversion gain MODIN - RFO 70 100 300 130 390 0.3 k W V 230 ETXO = 0; no load Highest operating frequency USA Base Channel 9 (US1b9) For the complete programming see behind section "channel frequencies, dividers and country settings" USA1: GMOD[1:0] = 00; fMod = ~7.6 MHz USA2: GMOD[1:0] = 01; fMod = ~5.7 MHz France: GMOD[1:0] = 01; fMod = 4.3 MHz GMOD[1:0] = 00; fMod = 4.3 MHz Spain/Netherlands: GMOD[1:0] = 10; fMod = 1.8 MHz 49.9900 MHz 5.2 kHz/V 5.2 kHz/V 3.8 2.7 kHz/V kHz/V 7.9 kHz/V
12 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
Parameters Demodulated distortion THD MODIN - RFO Test Conditions Modulation frequency: 1 kHz US: F = 4.0 kHz France: F = 2.5 kHz Symbol Min. Typ. 1.5 Max. 5 Unit %
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Remark: The tx conversion gain of the RF transmitter is somehow dependent on temperature. This is determined by the fundamental principle of this circuitry. Means have been taken inside the limiter amplifier, being in the signal path before MODIN, which are able to completely compensate this temperature behavior. Logical Part Inputs: C, D Low voltage input High voltage input Vil Vih Ii 0.2*VDD 0.8*VDD -1 -5 Input leakage current (0 < VI < VDD) Input leakage current Pin XCK (0 < VI < VDD) Serial bus (figure 8) Data set-up time Data hold time Clock low time Clock high time Hold time before transfer condition Data low pulse on transfer condition Data high pulse on transfer condition tsud thd tcl tch teon teh teoff +5 +5 A A 0.1 0 2 2 0.1 0.2 0.2 s s s s s s s
Fine Adjustment of the Oscillator Frequency
To set the frequency of the oscillator exact to 11.15 MHz, the frequency is adjustable in 8 steps, by adding 3 different internal capacities the frequency could be reduced.
AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A A AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A
FAOS2 FAOS1 FAOS0 0 0 1 0 1 0 1 0 0 1 1 1 100 200 400 700 Hz Rev.A1, 14-Jun-00 13 (34)
Parameters Oscillator frequency without reduction Changing of oscillator frequency with FOSC reduction
Test Conditions / Pins FAOS (0:2) = 0
Min.
Typ. 11.15 +D
Max.
Unit MHz
Preliminary Information
BZT55C51 RFO 56K 10N 24K 68N MIX1IN2
10N 10N
MIX1IN1
5P
44 LO1 LO2 GNDLO
MIX1O
PCLO RFOGND
330
10N
TX-/Modulator- Loop Filter MODIN 5.6K 1U DATA 470N 100N 10N VRF 470N NOTE: This schematics is only a basic(simplified) representation of the current production test circuit
RFO RFOVB AGND VBIAS VRF MLF LFGND MODIN VDD VSS DATA CLOCK DACO
MIX1IN1 MIX1O OSCGND XCK VAF MIX2O MIX2GND MIX2IN IFIN1
1 2
A A
1 0
MIX1IN2
VAF
470N 6.8P MIX2O
10N
IFIN2 ETC EIN RECO1 RECO2 RXO DAIN MIC MICO 23
1500 470N
CLOCK
OPOUT OPIN TXO LIMIN COUT CTC CIN 22
MIX2IN 10N
DACO
10N
IFIN1
470N
10K
10N
IFIN2
850 44K
220N
EIN
RECO1 4.7N 1000
22UF
RECO2
RXO
DAIN
Test Circuit
U3600BM
14 (34)
Figure 7. Test circuit
1
Preliminary Information
Rev.A1, 14-Jun-00
16257
RFOVB 470N 11.15M
U3600BM
MPU serial interface
10K 220N 47N 47N SPLAIN COUT OPOUT CIN COUT VDD LIMIN
85 MICIN
MICO
+VB
100n 47p CFW 450 E 4.7p 47p 11.15 MHz 100n 390 5.6k 100n 470n SFE 10.7 MS 2
Duplex Filter
Antenna
Rev.A1, 14-Jun-00
100n
Application Circuit
RX
RXGND
41 39 35 28 Expander Ear Amp 27 Mixer2 RSSI
MUXDA
40 36 33 31 29 IF - Amp 32 Mixer1 Crystal Oscillator
38 37 34 30
42
68n
10n
220n
24K D A Demodulator - + 43 5.6p 44
fLO VCO3 fLO sin cos
Comparator 1 1 DATRX
56K
2x BZT55C51
:2
fLO :N Phase
fRef3
Serial Bus
26
1K 22n 20K 25
7.5K 100n 8.2K
:K
(3)
Hand : 100nH Base : 230nH
Bias Bat low Detector
+
0.75n
22n
15n
-
1.5V
TXGND
MixerT
+45 -45
-
Mic :D2 :D1 :M12 :M12 fMod fRef2 :2 : (PM + QM ) 223
24
2.2K
470n
+
:10
22K VRMIC 23 22 Compressor :M :2 21 470n
Electret Micro- phone
220n
Figure 8. Application circuit
(1)
:D3
TX (2)
100n 2 3 Comparator 1n 330
+VB
10
100n
Phase
Preliminary Information
fRef1
VCO1 8 9 10 20
1uH
2.2K
+
Phase
Comparator 11 12 13 14 15 16 Spl Amp1.5V
4.7K
VCO2
5 6 7
Loop Filter
4
-
Limiter 17
19
2.2n
12K 56n 18 100K
20
+VB
5.6K 1u 100n 10K
15n 1n 10K 12K
15K
TX DATA
12n 4.7n
(1): PLL1: Modulator PLL (2): PLL2: Mixer PLL (3): PLL3: Local oscillator (LO) PLL
U3600BM
DACO C D VDD
mC
15 (34)
U3600BM
Channel Frequencies, Dividers and Country Settings
To meet all requirements of various countries * France (F), Spain (E), Netherlands (NL), USA, Portugal (P), Taiwan, New Zealand and Korea * and modes * base (b), handset (h) * several bits have to be set which do not change for the different channels. These settings are called country settings. The country-setting bits contain: D Rough adjustments for 2 VCOs D Setting three integer divider in the mixer PLL and modulator PLL D Conversion gain adjustment of mixer PLL Name Registers RA1[1:0] RA2[1:0] D1[1:0] D20 M12 D3[1:0] KV[3:1] GMOD[1:0] IMIXI DR1[1:0] Function Rough adjust VCO1 Rough adjust VCO2 Integer divider D1 Integer divider D2 Integer divider M12 Integer divider D3 Conversion gain VCO2 Modulator gain Reverse inputs of PC of PLL Additional divider M for reference frequency fRef1 Frequency range Mixer T Demodulator gain D Modulator gain D Setting of the pulling direction of PLL2 (value dependent, if TX frequency is higher or lower than LO frequency) D Demodulator gain Notes 00: is the highest frequency 00: is the highest frequency Division by 2, 4, 6, 8 Division by 6, 8 Doubles reference frequency of PLL2 when set to "1" Division by 1, 2, 4 00: gain minimal 0: if fVCO2 lower than fVCO3 "0" means no reduction, >0 only necessary in E, NL, Portugal 0: output frequency < 5 MHz 0: high gain 1: low gain Number of Positions 3 4 4 2 2 3 6 3 2 4
FRMT GDEM
2 2
Note: Setting the fractional dividers: For N, QM, send the binary equivalent of the numbers given below. For PM (integer part of modulator PLL), send the D2 complement (16 - PM) i.e., Fb1 (PM = 7, QM = 159 => integer: send 16 - PM = 9, fractional: send 159)
16 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
Tables for Programming of the Dividers (Refer to Block Diagram)
Divider D1, for PLL2:
D11(bit) 0 0 1 1 D10(bit) 0 1 0 1 Decimally 0 1 2 3 D1 (Block Diagram), if M12 = 0 2 8 6 4 D1 (Block Diagram), if M12 = 1 1 4 3 2
Divider D2, between PLL1 and PLL2:
D20(bit) 0 0 Decimally 0 1 D2 (Block Diagram), if M12 = 0 6 8 D2 (Block Diagram), if M12 = 1 3 4
Divider D3, for PLL1:
D31(bit) 0 0 1 1 D30(bit) 0 1 0 1 Decimally 0 1 2 3 D3 (Block Diagram) 1 2 2 4
Divider M, for Reference Frequency of PLL1:
There are several countries like Spain, the Netherlands and Portugal with relatively low modulator frequencies fMod. In case of modulation there will be a big maximum time shift between pulses coming from fractional divider and pulses coming from reference frequency divider. As a consequence the phase comparator enters an undesired operation mode. To avoid entering this operation mode the reference frequency fRef1 has to be reduced by a factor M. Simultaneously, keeping fMod constant, the factors of fractional dividers have to be changed as well. The connection between the additional reference frequency divider M and the factors PM and QM of fractional divider is given below. The subscript M denotes which value of M refers to the factors PM and QM of fractional divider. The formulas take into account that the numerator of the fraction QM/223 must not exceed 223. PM = P1*M + integer (Q1*M/223) QM = Q1*M - 223*integer (Q1*M/223)
Rev.A1, 14-Jun-00
17 (34)
Preliminary Information
U3600BM
France Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 00 11 11 1 01 Value max min D1 = 4 D2 = 8 D3 = 2 KV2[3:1] 100 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 01 * 0 00 0 0 supra M=1 low high gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 26.3125 41.3125 30.6125 26.3250 41.3250 30.6250 26.3375 41.3375 30.6375 26.3500 41.3500 30.6500 26.3625 41.3625 30.6625 26.3750 41.3750 30.6750 26.3875 41.3875 30.6875 26.400 41.4000 30.7000 26.4125 41.4125 30.7125 26.4250 41.4250 30.7250 26.4375 41.4375 30.7375 26.4500 41.4500 30.7500 26.4625 41.4625 30.7625 26.4750 41.4750 30.7750 26.4875 41.4875 30.7875 DV3I[14:0] = N 4898 4900 4902 4904 4906 4908 4910 4912 4914 4916 4918 4920 4922 4924 4926
Remark: *) Alternatively, GMOD[1:0] could be set to "00". This reduces the TX conversion gain (MODIN --> RFO) from about 3.8 kHz/V to about 2.7 kHz/V, a value, which should be still sufficient for a maximum f of ~2.5 kHz that is useful in the French case.
France Modulation Loop Frequency and Divider
fMod = 4.3 MHz, PM = 7, QM = 159, M = 1
18 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
France Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 00 01 11 1 01 Value max D1 = 4 D2 = 8 D3 = 2 KV2[3:1] 101 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 01 * 1 00 0 0 infra M=1 low high gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 41.3125 26.3125 37.0125 41.3250 26.3250 37.0250 41.3375 26.3375 37.0375 41.3500 26.3500 37.0500 41.3625 26.3625 37.0625 41.3750 26.3750 37.0750 41.3875 26.3875 37.0875 41.4000 26.4000 37.1000 41.4125 26.4125 37.1125 41.4250 26.4250 37.1250 41.4375 26.4375 37.1375 41.4500 26.4500 37.1500 41.4625 26.4625 37.1625 41.4750 26.4750 37.1750 41.4875 26.4875 37.1875 DV3I[14:0] = N 5922 5924 5926 5928 5930 5932 5934 5936 5938 5940 5942 5944 5946 5948 5950
Remark: *) Alternatively, GMOD[1:0] could be set to "00". This reduces the TX conversion gain (MODIN --> RFO) from about 3.8 kHz/V to about 2.7 kHz/V, a value, which should be still sufficient for a maximum f of ~2.5 kHz that is useful in the French case.
France Modulation Loop Frequency and Divider
fMod = 4.3 MHz, PM = 7, QM = 159, M = 1
Rev.A1, 14-Jun-00
19 (34)
Preliminary Information
U3600BM
Spain Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 10 00 1 11 Value D1 = 2 D2 = 8 D3 = 4 KV2[3:1] 001 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 10 1 11 1 1 infra M=4 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 31.025 39.925 29.225 31.050 39.950 29.250 31.075 39.975 29.275 31.100 40.000 29.300 31.125 40.025 29.325 31.150 40.050 29.350 31.175 40.075 29.375 31.200 40.100 29.400 31.250 40.150 29.450 31.275 40.175 29.475 31.300 40.200 29.500 31.325 40.225 29.525 DV3I[14:0] = N 4676 4680 4684 4688 4692 4696 4700 4704 4712 4716 4720 4724
Spain Modulation Loop Frequency and Divider
fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4, PM = 12, QM = 204, M = 4
Spain Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 01 00 1 11 Value high D1 = 2 D2 = 8 D3 = 4 KV2[3:1] 100 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 10 0 11 1 1 high supra M=4 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 39.925 31.025 41.725 39.950 31.050 41.750 39.975 31.075 41.775 40.000 31.100 41.800 40.025 31.125 41.825 40.050 31.150 41.850 40.075 31.175 41.875 40.100 31.200 41.900 40.150 31.250 41.950 40.175 31.275 41.975 40.200 31.300 42.000 40.225 31.325 42.025 DV3I[14:0] = N 6676 6680 6684 6688 6692 6696 6700 6704 6712 6716 6720 6724
Spain Modulation Loop Frequency and Divider
fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4, PM = 12, QM = 204, M = 4
20 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
Netherlands Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 10 00 1 11 Value low D1 = 2 D2 = 8 D3 = 4 KV2[3:1] 001 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 10 1 11 1 1 high infra M=4 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 31.0375 39.9375 29.2375 31.0625 39.9625 29.2625 31.0875 39.9875 29.2875 31.1125 40.0125 29.3125 31.1375 40.0375 29.3375 31.1625 40.0625 29.3625 31.1875 40.0875 29.3875 31.2125 40.1125 29.4125 31.2375 40.1375 29.4375 31.2625 40.1625 29.4625 31.2875 40.1875 29.4875 31.3125 40.2125 29.5125 DV3I[14:0] = N 4678 4682 4686 4690 4694 4698 4702 4706 4710 4714 4718 4722
Netherlands Modulation Loop Frequency and Divider
fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4, PM = 12, QM = 204, M = 4
Netherlands Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 01 00 1 11 Value high D1 = 2 D2 = 8 D3 = 4 KV2[3:1] 001 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 10 0 11 1 1 high supra M=4 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 39.9375 31.0375 41.7375 39.9625 31.0625 41.7625 39.9875 31.0875 41.7875 40.0125 31.1125 41.8125 40.0375 31.1375 41.8375 40.0625 31.1625 41.8625 40.0875 31.1875 41.8875 40.1125 31.2125 41.9125 40.1375 31.2375 41.9375 40.1625 31.2625 41.9625 40.1875 31.2875 41.9875 40.2125 31.3125 42.0125 DV3I[14:0] = N 6678 6682 6686 6690 6694 6698 6702 6706 6710 6714 6718 6722
Netherlands Modulation Loop Frequency and Divider
fRef1 = 557.5 kHz/4, fmod = 1.8 MHz/4, PM = 12, QM = 204, M = 4 Rev.A1, 14-Jun-00 21 (34)
Preliminary Information
U3600BM
U.K. Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 10 00 1 11 Value low D1 = 2 D2 = 8 D3 = 4 KV2[3:1] 001 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 10 1 11 1 1 high infra M=4 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 31.0375 39.9375 29.2375 31.0625 39.9625 29.2625 31.0875 39.9875 29.2875 31.1125 40.0125 29.3125 DV3I[14:0] = N 4678 4682 4686 4690
U.K. Modulation Loop Frequency and Divider
fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4, PM = 12, QM = 204, M = 4
U.K. Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 01 00 1 11 Value high D1 = 2 D2 = 8 D3 = 4 KV2[3:1] 001 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 10 0 11 1 1 high supra M=4 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 39.9375 31.0375 41.7375 39.9625 31.0625 41.7625 39.9875 31.0875 41.7875 40.0125 31.1125 41.8125 DV3I[14:0] = N 6678 6682 6686 6690
Netherlands Modulation Loop Frequency and Divider
fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4, PM = 12, QM = 204, M = 4
22 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
USA Base
Country setting channels (channel 1 - 10, USA1):
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 00 01 1 00 Value max D1 = 8 D2 = 8 D3 = 1 KV2[3:1] 100 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 00 1 00 1 1 low infra M=1 high low gain
Country setting new channels (channel 11 - 25, USA2):
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 01 01 10 0 00 Value high D1 = 6 D2 = 6 D3 = 1 KV2[3:1] 110 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 01 1 00 0 1 infra M=1 low low gain
Channel frequencies and 1st LO divider, fRef3 = 5 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 46.610 49.670 38.970 46.630 49.845 39.145 46.670 49.860 39.160 46.710 49.770 39.070 46.730 49.875 39.175 46.770 49.830 39.130 46.830 49.890 39.190 46.870 49.930 39.230 46.930 49.990 39.290 46.970 49.970 39.270 DV3I[14:0] = N 7794 7829 7832 7814 7835 7826 7838 7846 7858 7854
New channels
Channel Number 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 43.720 48.760 38.06 43.740 48.840 38.14 43.820 48.860 38.16 43.840 48.920 38.22 43.920 49.020 38.32 43.960 49.080 38.38 44.120 49.100 38.40 44.160 49.160 38.46 44.180 49.200 38.50 44.200 49.240 38.54 44.320 49.280 38.58 44.360 49.360 38.66 44.400 49.400 38.70 44.460 49.460 38.76 44.480 49.500 38.80 DV3I[14:0] = N 7612 7628 7632 7644 7664 7676 7680 7692 7700 7708 7716 7732 7740 7752 7760
Rev.A1, 14-Jun-00
23 (34)
Preliminary Information
U3600BM
USA Hand
Country setting channels (channel 1 - 10, USA1):
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 00 01 1 00 Value max D1 = 8 D2 = 8 D3 = 1 KV2[3:1] 100 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 00 0 00 1 1 supra M=1 high low gain
Country setting new channels (channel 11 - 25, USA2):
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 01 00 10 0 00 Value high D1 = 6 D2 = 6 D3 = 1 KV2[3:1] 110 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 01 0 00 0 1 supra M=1 low low gain
Channel frequencies and 1st LO divider, fRef3 = 5 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 49.670 46.610 57.31 49.845 46.630 57.33 49.860 46.670 57.37 49.770 46.710 57.41 49.875 46.730 57.43 49.830 46.770 57.47 49.890 46.830 57.53 49.930 46.870 57.57 49.990 46.930 57.63 49.970 46.970 57.67 DV3I[14:0] = N 11462 11466 11474 11482 11486 11494 11506 11514 11526 11534
New channels
Channel Number 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 48.760 43.720 54.42 48.840 43.740 54.44 48.860 43.820 54.52 48.920 43.840 54.54 49.020 43.920 54.62 49.080 43.960 54.66 49.100 44.120 54.82 49.160 44.160 54.86 49.200 44.180 54.88 49.240 44.200 54.90 49.260 44.320 55.02 49.360 44.360 55.06 49.400 44.400 55.10 49.460 44.460 55.16 49.500 44.480 55.18 DV3I[14:0] = N 10884 10888 10904 10908 10924 10932 10964 10972 10976 10980 11004 11012 11020 11032 11036
24 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
USA Modulation Loop Frequencies and Dividers
N Channel 1 2 3 4 5 6 7 8 9 10 New channels N Channel 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PM 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 QM 34 10 34 18 10 2 58 50 42 34 66 50 50 50 42 fMod (MHz) 5.66 5.60 5.66 5.62 5.60 5.58 5.72 5.70 5.68 5.66 5.74 5.70 5.70 5.70 5.68 PM 13 13 13 13 13 13 13 13 13 13 QM 157 95 105 157 123 157 157 157 157 181 fMod (MHz) 7.640 7.485 7.510 7.640 7.555 7.640 7.640 7.640 7.640 7.700
Rev.A1, 14-Jun-00
25 (34)
Preliminary Information
U3600BM
Portugal Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 01 10 00 1 11 Value D1 = 2 D2 = 8 D3 = 4 KV2[3:1] 001 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 10 1 11 1 1 infra M=4 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 27.550 37.000 26.300 27.575 37.025 26.325 27.600 37.050 26.350 27.625 37.075 26.375 27.650 37.100 26.400 27.675 37.125 26.425 27.700 37.150 26.450 27.725 37.175 26.475 27.750 37.200 26.500 27.775 37.225 26.525 27.800 37.250 26.550 27.825 37.275 26.575 DV3I[14:0] = N 4208 4212 4216 4220 4224 4228 4232 4236 4240 4244 4248 4252
Portugal Modulation Loop Frequency and Divider
fRef1 = 557.5 kHz/4, fMod = 1.25 MHz/4, PM = 8, QM = 216, M = 4
Portugal Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 01 01 00 1 11 Value D1 = 2 D2 = 8 D3 = 4 KV2[3:1] 001 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 10 0 11 1 1 supra M=4 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 37.000 27.550 38.250 37.025 27.575 38.275 37.050 27.600 38.300 37.075 27.625 38.325 37.100 27.650 38.350 37.125 27.675 38.375 37.150 27.700 38.400 37.175 27.725 38.425 37.200 27.750 38.450 37.225 27.775 38.475 37.250 27.800 38.500 37.275 27.825 38.525 DV3I[14:0] = N 6120 6124 6128 6132 6136 6140 6144 6148 6152 6156 6160 6164
Portugal Modulation Loop Frequency and Divider
fRef1 = 557.5 kHz/4, fMod = 1.25 MHz/4, PM = 8, QM = 216, M = 4
26 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
Taiwan Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 00 01 1 00 Value max D1 = 8 D2 = 8 D3 = 1 KV2[3:1] 110 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 01 1 00 1 1 infra M=1 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 45.2500 48.2500 37.5500 45.2750 48.2750 37.5750 45.3000 48.3000 37.6000 45.3250 48.3250 37.6250 45.3500 48.3500 37.6500 45.3750 48.3750 37.6750 45.4000 48.4000 37.7000 45.4250 48.4250 37.7250 45.4500 48.4500 37.7500 45.4750 48.4750 37.7750 DV3I[14:0] = N 6008 6012 6016 6020 6024 6028 6032 6036 6040 6044
Taiwan Modulation Loop Frequency and Divider
fMod = 7.7 MHz, PM = 13, QM = 181, M = 1
Taiwan Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 00 01 1 00 Value max D1 = 8 D2 = 8 D3 = 1 KV2[3:1] 110 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 00 0 00 1 1 supra M=1 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 48.2500 45.2500 55.9500 48.2750 45.2750 55.9750 48.3000 45.3000 56.0000 48.3250 45.3250 56.0250 48.3500 45.3500 56.0500 48.3750 45.3750 56.0750 48.4000 45.4000 56.1000 48.4250 45.4250 56.1250 48.4500 45.4500 56.1500 48.4750 45.4750 56.1750 DV3I[14:0] = N 8952 8956 8960 8964 8968 8972 8976 8980 8984 8988
Taiwan Modulation Loop Frequency and Divider
fMod = 7.7 MHz, PM = 13, QM = 181, M = 1
Rev.A1, 14-Jun-00
27 (34)
Preliminary Information
U3600BM
China Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 00 01 1 00 Value max D1 = 8 D2 = 8 D3 = 1 KV2[3:1] 110 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 01 1 00 1 1 infra M=1 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 45.0000 48.0000 37.3000 45.0250 48.0250 37.3250 45.0500 48.0500 37.3500 45.0750 48.0750 37.3750 45.1000 48.1000 37.4000 45.1250 48.1250 37.4250 45.1500 48.1500 37.4500 45.1750 48.1750 37.4750 45.2000 48.2000 37.5000 45.2250 48.2250 37.5250 45.2500 48.2500 37.5500 45.2750 48.2750 37.5750 45.3000 48.3000 37.6000 45.3250 48.3250 37.6250 45.3500 48.3500 37.6500 45.3750 48.3750 37.6750 45.4000 48.4000 37.7000 45.4250 48.4250 37.7250 45.4500 48.4500 37.7500 45.4750 48.4750 37.7750 DV3I[14:0] = N 5968 5972 5976 5980 5984 5988 5992 5996 6000 6004 6008 6012 6016 6020 6024 6028 6032 6036 6040 6044
China Modulation Loop Frequency and Divider
fMod = 7.7 MHz, PM = 13, QM = 181, M = 1
28 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
China Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 00 01 1 00 Value max D1 = 8 D2 = 8 D3 = 1 KV2[3:1] 110 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 00 0 00 1 1 supra M=1 high low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 48.000 45.0000 55.7000 48.0250 45.0250 55.7250 48.0500 450500 55.7500 48.0750 450750 55.7750 48.1000 45.1000 55.8000 48.1250 45.1250 55.8250 48.1500 45.1500 55.8500 48.1750 45.1750 55.8750 48.2000 45.2000 55.9000 48.2250 45.2250 55.9250 48.2500 45.2500 55.9500 48.2750 45.2750 55.9750 48.3000 45.3000 56.0000 48.3250 45.3250 56.0250 48.3500 45.3500 56.0500 48.3750 45.3750 56.0750 48.4000 45.4000 56.1000 48.4250 45.4250 56.1250 48.4500 45.4500 56.1500 48.4750 45.4750 56.1750 DV3I[14:0] = N 8912 8916 8920 8924 8928 8932 8936 8940 8944 8948 8952 8956 8960 8964 8968 8972 8976 8980 8984 8988
China Modulation Loop Frequency and Divider
fMod = 7.7 MHz, PM = 13, QM = 181, M = 1
Rev.A1, 14-Jun-00
29 (34)
Preliminary Information
U3600BM
New Zealand Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 00 01 11 1 01 Value max D1 = 4 D2 = 8 D3 = 2 KV2[3:1] 110 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 01 1 00 0 1 infra M=1 low low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 11 12 13 14 15 16 17 18 19 20 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 34.2500 40.2500 29.5500 34.2750 40.2750 29.5750 34.3000 40.3000 29.6000 34.3250 40.3250 29.6250 34.3500 40.3500 29.6500 34.3750 40.3750 29.6750 34.4000 40.4000 29.7000 34.4250 40.4250 29.7250 34.4500 40.4500 29.7500 34.4750 40.4750 29.7750 DV3I[14:0] = N 4728 4732 4736 4740 4744 4748 4752 4756 4760 4764
New Zealand Modulation Loop Frequency and Divider
fMod = 4.7 MHz, PM = 8, QM = 96, M = 1
New Zealand Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 00 01 11 1 01 Value max min D1 = 4 D2 = 8 D3 = 2 KV2[3:1] 101 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 01 0 00 0 1 supra M=1 low low gain
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number 11 12 13 14 15 16 17 18 19 20 TX Channel Frequency (MHz) RX Channel Frequency (MHz) 40.2500 40.2750 40.3000 40.3250 40.3500 40.3750 40.4000 40.4250 40.4500 40.4750 34.2500 34.2750 34.3000 34.3250 34.3500 34.3750 34.4000 34.4250 34.4500 34.4750 fLO = 1/2 fVCO3 (MHz) 44.9500 44.9750 45.0000 45.0250 45.0500 45.0750 45.1000 45.1250 45.1500 45.1750 DV3I[14:0] = N 7192 7196 7200 7204 7208 7212 7216 7220 7224 7228
New Zealand Modulation Loop Frequency and Divider
fMod = 4.7 MHz, PM = 8, QM = 96, M = 1
30 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
Korea Base
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Setting 10 00 01 1 00 Value max D1 = 8 D2 = 8 D3 = 1 KV2[3:1] 100 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 00 1 00 1 1 infra M=1 high low gain
Channel frequencies and 1st LO divider, fRef3 = 5 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 46.6100 49.6700 38.9700 46.6300 49.8450 39.1450 46.6700 49.8600 39.1600 46.7100 49.7700 39.0700 46.7300 49.8750 39.1750 46.7700 49.8300 39.1300 46.8300 49.8900 39.1900 46.8700 49.9300 39.2300 46.9300 49.9900 39.2900 46.9700 49.9700 39.2700 46.5100 49.6950 39.9950 46.5300 49.7100 39.0100 46.5500 49.7250 39.0250 46.5700 49.7400 39.0400 46.5900 49.7550 39.0550 DV3I[14:0] = N 7794 7829 7832 7814 7835 7826 7838 7846 7858 7854 7799 7802 7805 7808 7811
Korea Hand
Country setting:
Name RA1[1:0] RA2[1:0] D1[1:0] D20 D3[1:0] Value 10 00 01 1 00 Setting max D1 = 8 D2 = 8 D3 = 1 KV2[3:1] 100 GMOD[1:0] IMIXI DR1I[1:0] FRMT GDEM 00 0 00 1 1 supra M=1 high low gain
Channel frequencies and 1st LO divider, fRef3 = 5 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX Channel Frequency (MHz) RX Channel Frequency (MHz) fLO = 1/2 fVCO3 (MHz) 49.6700 46.6100 57.3100 49.8450 46.6300 57.3300 49.8600 46.6700 57.3700 49.7700 46.7100 57.4100 49.8750 46.7300 57.4300 49.8300 46.7700 57.4700 49.8900 46.8300 57.5300 49.9300 46.8700 57.5700 49.9900 46.9300 57.6300 49.9700 46.9700 57.6700 49.6950 46.5100 57.2100 49.7100 46.5300 57.2300 49.7250 46.5500 57.2500 49.7400 46.5700 57.2700 49.7550 46.5900 57.2900 DV3I[14:0] = N 11462 11466 11474 11482 11486 11494 11506 11514 11526 11534 11442 11446 11450 11454 11458
Rev.A1, 14-Jun-00
31 (34)
Preliminary Information
U3600BM
Korea Modulation Loop Frequencies and Dividers
N Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PM 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 QM 157 95 105 157 123 157 157 157 157 181 107 109 111 113 115 fMod (MHz) 7.640 7.485 7.510 7.640 7.555 7.640 7.640 7.640 7.640 7.700 7.515 7.520 7.525 7.530 7.535
32 (34)
Rev.A1, 14-Jun-00
Preliminary Information
U3600BM
Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications 13040
1
22
Rev.A1, 14-Jun-00
33 (34)
Preliminary Information
U3600BM
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
1.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
34 (34)
Rev.A1, 14-Jun-00
Preliminary Information

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